The invention relates to an electronic flip-flop circuit, having a data input, a data output, and a clock signal input, and comprising a first transfer gate for transferring, under the control of the clock signal, data from the data input to an input of a first storage element, and a second transfer gate for transferring, under the control of the clock signal, data from an output of the first storage element to an input of a second storage element, an output of which constitutes the data output, the transfer gates being directly driven by the same clock signal.
The invention also relates to an integrated circuit comprising such an electronic tip-flop circuit.
An electronic flip-flop circuit of this kind is known from U.S. Pat. No. 4,390,987. The prior-art circuit described therein with reference to FIG. 1 comprises a first transfer gate in the form of a pMOS transistor 22 and a second transfer gate in the form of an nMOS transistor 34, both transistors being driven by a clock signal 46. When the flip-flop circuit is very fast in relation to the edges of the clock signal, a transparent state will arise halfway along an edge of the clock signal: the data on the data input of the flip-flop circuit is transferred directly to the data output. This implies an incorrect logic state in the circuit including the flip-flop circuit. So-called "clock skew" can also give rise to an incorrect logic state. This is because when two series-connected flip-flop circuits are driven by two clock signals via different clock paths, it may occur that a clock pulse of the clock signal of the second flip-flop arrives slightly later than a corresponding clock pulse of the clock signal of the first flip-flop. The first flip-flop then assumes a next logic state while the second flip-flop has not yet fully assumed the current logic state. Thus, the second flip-flop prematurely assumes the next logic state. Furthermore, the known flip-flop circuit has the significant drawback that the pMOS transistor 22 has a high threshold voltage loss.